This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-203649, filed Jul. 4, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same, in particular, a semiconductor memory which reduces current consumption and narrow channel effect and a method of manufacturing the same.
2. Description of the Related Art
Generally, flash memories have memory cells, and various delay circuits and a writing/erasing high-voltage stabilizing circuit and the like necessary for its operation, inside a chip. Therefore, resistors and devices such as transistors which constitute their peripheral circuits are also formed inside the chip.
When a flash memory having a structure as described above is manufactured, increasing the manufacturing efficiency is required to reduce the manufacturing cost. Therefore, it increases the efficiency to manufacture cell transistors constituting memory cells and transistors constituting peripheral circuits by using almost the same manufacturing process.
FIGS. 12 to 17 show a conventional method of manufacturing a flash memory in sequential order. As shown in FIG. 12, the flash memory has a memory cell array region (hereinafter referred to as xe2x80x9ccell regionxe2x80x9d) and a region in which transistors of peripheral circuits are formed (hereinafter referred to as xe2x80x9cperipheral regionxe2x80x9d), on a semiconductor substrate. In the peripheral region, N channel MOSFETs (Metal Oxide Semiconductor Filed Effect Transistor) and P channel MOSFETs are formed.
A P well region 22 is formed on a surface of a semiconductor substrate 21, and thereafter an N well region 23 is formed in a part of the P well region 22 in which P channel MOSs of the peripheral region are formed. Then, a gate insulating film 24 is formed on the whole surface of the semiconductor substrate 21, and a first gate material 25 is formed on the gate insulating film 24. A silicon nitride film 26 and a silicon oxide film (not shown) are sequentially deposited on the first gate material 25. The silicon oxide film, silicon nitride film 26, first gate material 25 and gate oxide film 24 are etched by photolithography. The remaining silicon oxide film is removed.
As shown in FIG. 13, the surface of the semiconductor substrate 21 is etched with the silicon nitride film 26 used as a mask, forming trenches 27.
As shown in FIG. 14, inner walls of the trenches 27 are oxidized, and thereafter a silicon oxide film 28 serving as a device-isolating insulating film is deposited on the whole surface of the semiconductor device, and the silicon oxide film 28 is flattened. The silicon nitride film 26 is removed by wet etching, forming device-isolating regions comprising the silicon oxide film 28.
As shown in FIG. 15, a second gate material 29 is deposited on the whole surface of the semiconductor device. The second gate material 29 is provided directly on the first gate material 25. The first gate material 25 and the second gate material 29 constitute a floating gate of a memory cell in a later step. The second gate material 29 on the silicon oxide film 28 in the cell region is etched by photolithography, forming a slit 30 in the second gate material 29 on each silicon oxide film 28. The slit 30 isolates a floating gate for each memory cell from others. A photoresist used in the photolithography is removed.
As shown in FIG. 16, an ONO film 31 comprising a silicon oxide film, a silicon nitride film and a silicon oxide film is deposited on the whole surface of the semiconductor device.
In FIG. 17, a photoresist (not shown) is formed only in the cell region, by photolithography. With the photoresist used as a mask, the ONO film 31, the first gate material 25 and the second gate material 29 in the peripheral region are removed. Then, the gate oxide film 24 in the peripheral region is removed by wet etching using NH4F or the like, and thereafter the photoresist in the cell region is removed.
A gate insulating film for MOSFETs is formed in the peripheral region by a known method, and a polysilicon film, for example, is deposited on the whole surface of the semiconductor device. Then, the polysilicon film is etched by means of photolithography and anisotropic etching using RIE, and thereby control gates and floating gates are formed in the cell region.
Gate electrodes of MOSFETs are formed by photolithography and anisotropic etching using RIE. Then, post oxidation is performed.
Impurities are diffused in the cell region and the peripheral region, forming source and drain regions. Then, gate sidewalls are formed, and thereafter a salicide is formed on the gate electrode and the semiconductor substrate of the thus-formed diffusion layer. A silicon nitride film and a BPSG (Boron Doped Phospho-Silicate Glass) are coated on the whole surface of the semiconductor device.
Contact holes are formed by photolithography and RIE, and an Al wiring film is deposited thereon by sputtering or the like. After a wiring pattern is formed by photolithography and RIE, a PSG (Phospho-Silicate Glass) is deposited to protect the Al wiring. Then, a silicon nitride film is deposited, and the PSG n a bonding pad is removed by etching to complete the device as a wafer.
As described above, the gate insulating film 24 on the peripheral region is removed by wet etching. Therefore, as shown in FIG. 17, etching solution entering between each of the silicon oxide film 28 and the semiconductor substrate 21 etches the silicon oxide films 28, and thereby edge portions of the silicon oxide films 28 are also reduced. This generates a gap between each silicon oxide film 28 and the semiconductor substrate 21. When gate electrodes are deposited in the following step, a gate electrode material is embedded in the gaps. Electric field concentrates in the parts in which the gate electrode material is embedded. Therefore, kink property appears in subthreshold characteristics, which increases the current consumed by the MOSFET including the gate electrode. Further, this causes the problem that the narrow channel effect of the MOSFET becomes more significant and thereby the operation speed of the MOSFET decreases.
A method of manufacturing a semiconductor memory, having a cell region in which a cell transistor is formed and a peripheral region in which peripheral transistor of peripheral circuit is formed, according to a first aspect of the present invention comprises forming a gate oxide film, a first gate material and a first insulation film on a semiconductor substrate in the cell region and the peripheral region; forming a plurality of gate structures comprising the first insulation film, the first gate material and the gate oxide film in the cell region and the peripheral region, by etching a part of the first insulation film, the first gate material, and the gate oxide film; forming a second insulation film on side surfaces of the gate structures formed in the peripheral region; forming a plurality of trenches at a surface of the semiconductor substrate in the cell region and the peripheral region, by etching the semiconductor substrate with the first insulation film and the second insulation film used as masks; exposing the surface of the semiconductor substrate in the vicinity of the gate structures on both sides of the trenches, by removing the second insulation film on the side surfaces of the gate structures formed in the peripheral region; forming element-isolating insulation films in the trenches in the cell region, and in the trenches in the peripheral region such that the films extend onto the surface of the semiconductor substrate in the vicinity of the gate structures; removing the gate structures formed in the peripheral region; and forming gate structures of the peripheral transistors between the element-isolating insulation films of the peripheral region.
A semiconductor device according to a second aspect of the present invention comprises a cell transistor formed in a cell region; first element-isolating insulation films provided in trenches formed at a surface of a semiconductor substrate in the cell region; a peripheral transistor formed in a peripheral region; and second element-isolating insulation films provided in trenches formed at the surface of the semiconductor substrate in the peripheral region, the second element-isolating insulation film having different shape from the first element-isolating insulation film, and having rounded edge portions projecting from the semiconductor substrate.